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ICS
2001
Tsinghua U.
15 years 4 months ago
Slice-processors: an implementation of operation-based prediction
We describe the Slice Processor micro-architecture that implements a generalized operation-based prefetching mechanism. Operation-based prefetchers predict the series of operation...
Andreas Moshovos, Dionisios N. Pnevmatikatos, Amir...
SPAA
2009
ACM
16 years 10 days ago
A lightweight in-place implementation for software thread-level speculation
Thread-level speculation (TLS) is a technique that allows parts of a sequential program to be executed in parallel. TLS ensures the parallel program's behaviour remains true ...
Cosmin E. Oancea, Alan Mycroft, Tim Harris
IWAN
2000
Springer
15 years 3 months ago
A Flexible IP Active Networks Architecture
This paper presents the main concepts of the IST Project FAIN "Future Active IP Networks" [10], a three-year collaborative research project, whose main task is to develo...
Alex Galis, Bernhard Plattner, Jonathan M. Smith, ...
BMCBI
2008
211views more  BMCBI 2008»
14 years 12 months ago
CUDA compatible GPU cards as efficient hardware accelerators for Smith-Waterman sequence alignment
Background: Searching for similarities in protein and DNA databases has become a routine procedure in Molecular Biology. The Smith-Waterman algorithm has been available for more t...
Svetlin Manavski, Giorgio Valle
PODC
2000
ACM
15 years 4 months ago
Garbage collection of timestamped data in Stampede
Stampede is a parallel programming system to facilitate the programming of interactive multimedia applications on clusters of SMPs. In a Stampede application, a variable number of...
Rishiyur S. Nikhil, Umakishore Ramachandran