Multiple memory models have been proposed to capture the effects of memory hierarchy culminating in the I-O model of Aggarwal and Vitter [?]. More than a decade of architectural a...
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence betwe...
This paper presents an analytical method for the performability evaluation of a previously reported network memory server attached to a local area network. To increase the perform...
Orhan Gemikonakli, Glenford E. Mapp, Enver Ever, D...
We test a selection of associative memory models built with different connection strategies, exploring the relationship between the structural properties of each network and its pa...
Lee Calcraft, Rod Adams, Weiliang Chen, Neil Davey
We present a class of relaxed memory models, defined in Coq, parameterised by the chosen permitted local reorderings of reads and writes, and the visibility of inter- and intra-pr...
Jade Alglave, Luc Maranget, Susmit Sarkar, Peter S...