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ISCAS
2005
IEEE
154views Hardware» more  ISCAS 2005»
15 years 10 months ago
An automated methodology for memory-conscious mapping of DSP applications on coarse-grain reconfigurable arrays
—This paper presents a memory-conscious mapping methodology of computational intensive applications on coarse-grain reconfigurable arrays. By exploiting the inherent abundant amo...
Michalis D. Galanis, Gregory Dimitroulakos, Consta...
SOFTVIS
2005
ACM
15 years 10 months ago
Adding parallelism to visual data flow programs
Programming in parallel is an error-prone and complex task compounded by the lack of tool support for both programming and debugging. Recent advances in compiler-directed shared m...
Philip T. Cox, Simon Gauvin, Andrew Rau-Chaplin
DATE
2003
IEEE
154views Hardware» more  DATE 2003»
15 years 9 months ago
Packetized On-Chip Interconnect Communication Analysis for MPSoC
Interconnect networks play a critical role in shared memory multiprocessor systems-on-chip (MPSoC) designs. MPSoC performance and power consumption are greatly affected by the pac...
Terry Tao Ye, Luca Benini, Giovanni De Micheli
DATE
2002
IEEE
114views Hardware» more  DATE 2002»
15 years 9 months ago
A Video Compression Case Study on a Reconfigurable VLIW Architecture
In this paper, we investigate the benefits of a flexible, application-specific instruction set by adding a run-time Reconfigurable Functional Unit (RFU) to a VLIW processor. Preli...
Davide Rizzo, Osvaldo Colavin
WSC
1997
15 years 5 months ago
Modeling a 10 Gbit/s/Port Shared Memory ATM Switch
The speed of optical transmission links is growing at a rate which is difficult for the micro-electronic technology of ATM switches to follow. In order to cover the transmission r...
Tawfik Lazraq, Jakob Brundin, Per Andersson, &Arin...