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ISCA
2011
IEEE
294views Hardware» more  ISCA 2011»
14 years 3 months ago
Moguls: a model to explore the memory hierarchy for bandwidth improvements
In recent years, the increasing number of processor cores and limited increases in main memory bandwidth have led to the problem of the bandwidth wall, where memory bandwidth is b...
Guangyu Sun, Christopher J. Hughes, Changkyu Kim, ...
GLVLSI
2007
IEEE
154views VLSI» more  GLVLSI 2007»
15 years 6 months ago
A design kit for a fully working shared memory multiprocessor on FPGA
This paper presents a framework to design a shared memory multiprocessor on a programmable platform. We propose a complete flow, composed by a programming model and a template ar...
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo...
DATE
2002
IEEE
84views Hardware» more  DATE 2002»
15 years 4 months ago
Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory
Multimedia applications are characterized by a large number of data accesses and complex array index manipulations. The built-in address decoder in the RAM memory model commonly u...
Sambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas...
VLSID
2007
IEEE
133views VLSI» more  VLSID 2007»
16 years 3 days ago
On the Impact of Address Space Assignment on Performance in Systems-on-Chip
Today, VLSI systems for computationally demanding applications are being built as Systems-on-Chip (SoCs) with a distributed memory sub-system which is shared by a large number of ...
G. Hazari, Madhav P. Desai, H. Kasture
ESOP
2010
Springer
15 years 9 months ago
Parameterized Memory Models and Concurrent Separation Logic
Formal reasoning about concurrent programs is usually done with the assumption that the underlying memory model is sequentially consistent, i.e. the execution outcome is equivalen...
Rodrigo Ferreira, Xinyu Feng and Zhong Shao