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109
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ISCA
1996
IEEE
99views Hardware» more  ISCA 1996»
15 years 7 months ago
High-Bandwidth Address Translation for Multiple-Issue Processors
In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing ...
Todd M. Austin, Gurindar S. Sohi
174
Voted
SPAA
1996
ACM
15 years 7 months ago
From AAPC Algorithms to High Performance Permutation Routing and Sorting
Several recent papers have proposed or analyzed optimal algorithms to route all-to-all personalizedcommunication (AAPC) over communication networks such as meshes, hypercubes and ...
Thomas Stricker, Jonathan C. Hardwick
148
Voted
CF
2007
ACM
15 years 7 months ago
An analysis of the effects of miss clustering on the cost of a cache miss
In this paper we describe a new technique, called pipeline spectroscopy, and use it to measure the cost of each cache miss. The cost of a miss is displayed (graphed) as a histogra...
Thomas R. Puzak, Allan Hartstein, Philip G. Emma, ...
113
Voted
ATAL
2006
Springer
15 years 7 months ago
Verifying space and time requirements for resource-bounded agents
The effective reasoning capability of an agent can be defined as its capability to infer, within a given space and time bound, facts that are logical consequences of its knowledge...
Natasha Alechina, Mark Jago, Piergiorgio Bertoli, ...
131
Voted
SC
1995
ACM
15 years 7 months ago
Lazy Release Consistency for Hardware-Coherent Multiprocessors
Release consistency is a widely accepted memory model for distributed shared memory systems. Eager release consistency represents the state of the art in release consistent protoc...
Leonidas I. Kontothanassis, Michael L. Scott, Rica...