Sciweavers

2756 search results - page 47 / 552
» Computation-Centric Memory Models
Sort
View
ISCA
2007
IEEE
126views Hardware» more  ISCA 2007»
15 years 10 months ago
Comparing memory systems for chip multiprocessors
There are two basic models for the on-chip memory in CMP systems: hardware-managed coherent caches and software-managed streaming memory. This paper performs a direct comparison o...
Jacob Leverich, Hideho Arakida, Alex Solomatnikov,...
IPPS
2010
IEEE
15 years 1 months ago
Parallel external memory graph algorithms
In this paper, we study parallel I/O efficient graph algorithms in the Parallel External Memory (PEM) model, one of the private-cache chip multiprocessor (CMP) models. We study the...
Lars Arge, Michael T. Goodrich, Nodari Sitchinava
ETS
2007
IEEE
91views Hardware» more  ETS 2007»
15 years 10 months ago
PPM Reduction on Embedded Memories in System on Chip
This paper summarizes advanced test patterns designed to target dynamic and time-related faults caused by new defect mechanisms in deep-submicron memory technologies. Such tests a...
Said Hamdioui, Zaid Al-Ars, Javier Jiménez,...
APSEC
2008
IEEE
15 years 10 months ago
A Heap Model for Java Bytecode to Support Separation Logic
Memory usage analysis is an important problem for resource-constrained mobile devices, especially under mission- or safety-critical circumstances. Program codes running on or bein...
Chenguang Luo, Guanhua He, Shengchao Qin
SAC
2006
ACM
15 years 9 months ago
Building the functional performance model of a processor
In this paper, we present an efficient procedure for building a piecewise linear function approximation of the speed function of a processor with hierarchical memory structure. Th...
Alexey L. Lastovetsky, Ravi Reddy, Robert Higgins