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ASAP
2005
IEEE
169views Hardware» more  ASAP 2005»
15 years 9 months ago
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
Grigoris Dimitroulakos, Michalis D. Galanis, Costa...
ACMMSP
2005
ACM
106views Hardware» more  ACMMSP 2005»
15 years 9 months ago
Impact of modern memory subsystems on cache optimizations for stencil computations
In this work we investigate the impact of evolving memory system features, such as large on-chip caches, automatic prefetch, and the growing distance to main memory on 3D stencil ...
Shoaib Kamil, Parry Husbands, Leonid Oliker, John ...
WMPI
2004
ACM
15 years 9 months ago
Understanding the effects of wrong-path memory references on processor performance
High-performance out-of-order processors spend a significant portion of their execution time on the incorrect program path even though they employ aggressive branch prediction al...
Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale ...
APCSAC
2003
IEEE
15 years 9 months ago
User-Level Management of Kernel Memory
Abstract. Kernel memory is a resource that must be managed carefully in order to ensure the efficiency and safety of the system. The use of an inappropriate management policy can w...
Andreas Haeberlen, Kevin Elphinstone
IPPS
2000
IEEE
15 years 8 months ago
The Memory Bandwidth Bottleneck and its Amelioration by a Compiler
As the speed gap between CPU and memory widens, memory hierarchy has become the primary factor limiting program performance. Until now, the principal focus of hardware and softwar...
Chen Ding, Ken Kennedy