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ICCAD
2006
IEEE
127views Hardware» more  ICCAD 2006»
15 years 6 months ago
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...
Murari Mani, Ashish Kumar Singh, Michael Orshansky
ICSE
2009
IEEE-ACM
15 years 4 months ago
MINTS: A general framework and tool for supporting test-suite minimization
Regression test suites tend to grow over time as new test cases are added to exercise new functionality or to target newly-discovered faults. When test suites become too large, th...
Hwa-You Hsu, Alessandro Orso
IEEEPACT
2007
IEEE
15 years 3 months ago
JudoSTM: A Dynamic Binary-Rewriting Approach to Software Transactional Memory
With the advent of chip-multiprocessors, we are faced with the challenge of parallelizing performance-critical software. Transactional memory (TM) has emerged as a promising progr...
Marek Olszewski, Jeremy Cutler, J. Gregory Steffan
SECON
2007
IEEE
15 years 3 months ago
A SoC-based Sensor Node: Evaluation of RETOS-enabled CC2430
—Recent progress in Wireless Sensor Networks technology has enabled many complicated real-world applications. Some of the applications demand a non-trivial amount of computation;...
Sukwon Choi, Hojung Cha, SungChil Cho
LCPC
2007
Springer
15 years 3 months ago
Associative Parallel Containers in STAPL
The Standard Template Adaptive Parallel Library (stapl) is a parallel programming framework that extends C++ and stl with support for parallelism. stapl provides a collection of pa...
Gabriel Tanase, Chidambareswaran Raman, Mauro Bian...