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ICCAD
2006
IEEE
108views Hardware» more  ICCAD 2006»
16 years 26 days ago
Soft error reduction in combinational logic using gate resizing and flipflop selection
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
Rajeev R. Rao, David Blaauw, Dennis Sylvester
LCPC
2007
Springer
15 years 10 months ago
Associative Parallel Containers in STAPL
The Standard Template Adaptive Parallel Library (stapl) is a parallel programming framework that extends C++ and stl with support for parallelism. stapl provides a collection of pa...
Gabriel Tanase, Chidambareswaran Raman, Mauro Bian...
SMA
2005
ACM
132views Solid Modeling» more  SMA 2005»
15 years 9 months ago
Simplified engineering analysis via medial mesh reduction
Numerous simplification methods have been proposed for speeding up engineering analysis/ simulation. A recently proposed medial axis reduction is one such method, that is particul...
Murari Sinha, Krishnan Suresh
IPPS
2000
IEEE
15 years 8 months ago
Run-Time Support for Adaptive Load Balancing
Abstract. Many parallel scienti c applications have dynamic and irregular computational structure. However, most such applications exhibit persistence of computational load and com...
Milind A. Bhandarkar, Robert Brunner, Laxmikant V....
GIS
2008
ACM
16 years 5 months ago
Parallel ODETLAP for terrain compression and reconstruction
We introduce a parallel approximation of an Over-determined Laplacian Partial Differential Equation solver (ODETLAP) applied to the compression and restoration of terrain data use...
Jared Stookey, Zhongyi Xie, Barbara Cutler, W. Ran...