Sciweavers

4217 search results - page 832 / 844
» Computational indistinguishability logic
Sort
View
DFG
2004
Springer
15 years 1 months ago
Modeling and Formal Verification of Production Automation Systems
This paper presents the real-time model checker RAVEN and related theoretical background. RAVEN augments the efficiency of traditional symbolic model checking with possibilities to...
Jürgen Ruf, Roland J. Weiss, Thomas Kropf, Wo...
FCCM
2004
IEEE
118views VLSI» more  FCCM 2004»
15 years 1 months ago
Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor
Reconfigurable System-on-Chip (SoC) platforms that incorporate hard-core processors surrounded by large amounts of FPGA are today commodities: the reconfigurable logic is often us...
Miljan Vuletic, Laura Pozzi, Paolo Ienne
FCCM
2004
IEEE
152views VLSI» more  FCCM 2004»
15 years 1 months ago
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor
Dynamically Reconfigurable Processor (DRP)[1] developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixte...
Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki...
DOLAP
2006
ACM
15 years 1 months ago
Building a web warehouse for accessibility data
As more and more information is available on the web, it is a problem that many web resources are not accessible, i.e., are not usable for users with special needs. For example, f...
Christian Thomsen, Torben Bach Pedersen
89
Voted
EMSOFT
2006
Springer
15 years 1 months ago
Analysis of the zeroconf protocol using UPPAAL
We report on a case study in which the model checker Uppaal is used to formally model parts of Zeroconf, a protocol for dynamic configuration of IPv4 link-local addresses that has...
Biniam Gebremichael, Frits W. Vaandrager, Miaomiao...