Many current designs contain a large number of standard cells intermixed with larger macro blocks. The range of size in these “mixed block” designs complicates the placement p...
Ateen Khatkhate, Chen Li 0004, Ameya R. Agnihotri,...
Compared with on-chip routers, the existing commercial tools for off-chip routing have a much lower routability and often result in a large number of unrouted nets for manual rout...
Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He...
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...
We present a domain-specific approach to representing datapaths for hardware implementations of linear signal transform algorithms. We extend the tensor structure for describing l...
Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during g...