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DAC
2007
ACM
15 years 10 months ago
Modeling the Function Cache for Worst-Case Execution Time Analysis
Static worst-case execution time (WCET) analysis is done by modeling the hardware behavior. In this paper we describe a WCET analysis technique to analyze systems with function ca...
Raimund Kirner, Martin Schoeberl
DAC
2006
ACM
15 years 10 months ago
Formal analysis of hardware requirements
Formal languages are increasingly used to describe the functional requirements (specifications) of circuits. These requirements are used as a means to communicate design intent an...
Ingo Pill, Simone Semprini, Roberto Cavada, Marco ...
GLVLSI
2009
IEEE
150views VLSI» more  GLVLSI 2009»
15 years 4 months ago
Contradictory antecedent debugging in bounded model checking
In the context of formal verification Bounded Model Checking (BMC) has shown to be very powerful for large industrial designs. BMC is used to check whether a circuit satisfies a...
Daniel Große, Robert Wille, Ulrich Kühn...
DAC
2009
ACM
15 years 10 months ago
Speculation in elastic systems
Speculation is a well-known technique for increasing parallelism of the microprocessor pipelines and hence their performance. While implementing speculation in modern design pract...
Marc Galceran Oms, Jordi Cortadella, Michael Kishi...
DAC
2007
ACM
15 years 10 months ago
SODA: Sensitivity Based Optimization of Disk Architecture
Storage plays a pivotal role in the performance of many applications. Optimizing disk architectures is a design-time as well as a run-time issue and requires balancing between per...
Yan Zhang, Sudhanva Gurumurthi, Mircea R. Stan