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DAC
2005
ACM
15 years 11 months ago
Full-chip analysis of leakage power under process variations, including spatial correlations
In this paper, we present a method for analyzing the leakage current, and hence the leakage power, of a circuit under process parameter variations that can include spatial correla...
Hongliang Chang, Sachin S. Sapatnekar
DAC
2005
ACM
15 years 11 months ago
Architecture-adaptive range limit windowing for simulated annealing FPGA placement
Previous research has shown both theoretically and practically that simulated annealing can greatly benefit from the incorporation of an adaptive range limiting window to control ...
Kenneth Eguro, Scott Hauck, Akshay Sharma
DAC
2006
ACM
15 years 11 months ago
Guiding simulation with increasingly refined abstract traces
Traces Kuntal Nanshi, Fabio Somenzi University of Colorado at Boulder ne abstraction refinement and simulation to provide a more efficient approach to checking invariant properti...
Kuntal Nanshi, Fabio Somenzi
DAC
2006
ACM
15 years 11 months ago
Synthesis of high-performance packet processing pipelines
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the featur...
Cristian Soviani, Ilija Hadzic, Stephen A. Edwards
GLVLSI
2006
IEEE
124views VLSI» more  GLVLSI 2006»
15 years 4 months ago
Dominator-based partitioning for delay optimization
Most of the logic synthesis algorithms are not scalable for large networks and, for this reason, partitioning is often applied. However traditional mincut-based partitioning techn...
David Bañeres, Jordi Cortadella, Michael Ki...