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DAC
2002
ACM
15 years 11 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...
DAC
2009
ACM
15 years 1 months ago
RegPlace: a high quality open-source placement framework for structured ASICs
Structured ASICs have recently emerged as an exciting alternative to ASIC or FPGA design style as they provide a new trade-off between the high performance of ASIC design and low ...
Ashutosh Chakraborty, Anurag Kumar, David Z. Pan
WETICE
2000
IEEE
15 years 1 months ago
Developing and Evaluating Collaborative Engineering Studios
We discuss a vision of and work in progress on a collaborative engineering environment, the Collaborative Design Studio, being developed at the Geometric and Intelligent Computing...
Jonathan Sevy, Vera Zaychik, Thomas T. Hewett, Wil...
DAC
2005
ACM
14 years 12 months ago
Keeping hot chips cool
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...
Ruchir Puri, Leon Stok, Subhrajit Bhattacharya
CHI
2011
ACM
14 years 1 months ago
Creek watch: pairing usefulness and usability for successful citizen science
Citizen science projects can collect a wealth of scientific data, but that data is only helpful if it is actually used. While previous citizen science research has mostly focused ...
Sunyoung Kim, Christine Robson, Thomas Zimmerman, ...