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DAC
2005
ACM
14 years 12 months ago
Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits
In this paper, we analyze the effect of jitter in track and hold circuits. The output spectrum is obtained in terms of the system function of the track and hold. It is a fairly g...
V. Vasudevan
DAC
2010
ACM
14 years 10 months ago
Automatic multithreaded pipeline synthesis from transactional datapath specifications
We present a technique to automatically synthesize a multithreaded in-order pipeline from a high-level unpipelined datapath specification. This work extends the previously propose...
Eriko Nurvitadhi, James C. Hoe, Shih-Lien Lu, Timo...
IJON
2010
127views more  IJON 2010»
14 years 8 months ago
Oscillation in a network model of neocortex
A basic understanding of the relationship between activity of individual neurons and macroscopic electrical activity of local field potentials or electroencephalogram (EEG) may pro...
Jennifer Dwyer, Hyong Lee, Amber Martell, Rick L. ...
ICCAD
2006
IEEE
108views Hardware» more  ICCAD 2006»
15 years 6 months ago
From molecular interactions to gates: a systematic approach
The continuous minituarization of integrated circuits may reach atomic scales in a couple of decades. Some researchers have already built simple computation engines by manipulatin...
Josep Carmona, Jordi Cortadella, Yousuke Takada, F...
DAC
2010
ACM
15 years 1 months ago
An efficient algorithm to verify generalized false paths
Timing exception verification has become a center of interest as incorrect constraints can lead to chip failures. Proving that a false path is valid or not is a difficult problem ...
Olivier Coudert