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DAC
2002
ACM
15 years 11 months ago
False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation
We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool ...
Jing-Jia Liou, Angela Krstic, Li-C. Wang, Kwang-Ti...
VLSID
2009
IEEE
223views VLSI» more  VLSID 2009»
15 years 10 months ago
Novel MOS Decoupling Capacitor Optimization Technique for Nanotechnologies
Designing MOS decoupling capacitors (DECAPs) in nanotechnologies provides many challenges due to the existing trade-offs among transient time response behavior, area, and gate lea...
Bardia Bozorgzadeh, Ali Afzali-Kusha
ISLPED
2007
ACM
117views Hardware» more  ISLPED 2007»
14 years 11 months ago
Power signal processing: a new perspective for power analysis and optimization
To address the productivity bottlenecks in power analysis and optimization of modern systems, we propose to treat power as a signal and leverage the rich set of signal processing ...
Quming Zhou, Lin Zhong, Kartik Mohanram
DAC
2005
ACM
15 years 11 months ago
Analysis of full-wave conductor system impedance over substrate using novel integration techniques
An efficient approach to full-wave impedance extraction is developed that accounts for substrate effects through the use of two-layer media Green's functions in a mixed-poten...
Xin Hu, Jung Hoon Lee, Jacob White, Luca Daniel
DAC
2005
ACM
15 years 11 months ago
Trace-driven HW/SW cosimulation using virtual synchronization technique
Poor performance of HW/SW cosimulation is mainly caused by synchronization requirement between component simulators. Virtual synchronization technique was proposed to remove the n...
Dohyung Kim, Youngmin Yi, Soonhoi Ha