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DAC
2009
ACM
16 years 7 months ago
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
Shiyan Hu, Zhuo Li, Charles J. Alpert
DAC
2004
ACM
16 years 7 months ago
Toward a methodology for manufacturability-driven design rule exploration
Resolution enhancement techniques (RET) such as optical proximity correction (OPC) and phase-shift mask (PSM) technology are deployed in modern processes to increase the fidelity ...
Luigi Capodieci, Puneet Gupta, Andrew B. Kahng, De...
DAC
2004
ACM
16 years 7 months ago
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...
Ashish Srivastava, Dennis Sylvester, David Blaauw
DAC
2005
ACM
16 years 7 months ago
Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design
In many of embedded systems, particularly for those with high data computations, the delay of memory access is one of the major bottlenecks in the system's performance. It ha...
Jungeun Kim, Taewhan Kim
MICCAI
2002
Springer
16 years 7 months ago
Line Integral Convolution for Visualization of Fiber Tract Maps from DTI
Abstract. Diffusion tensor imaging (DTI) can provide the fundamental information required for viewing structural connectivity. However, robust and accurate acquisition and processi...
Tim McGraw, Baba C. Vemuri, Zhizhou Wang, Yunmei C...
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