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HPCA
2006
IEEE
16 years 6 months ago
Completely verifying memory consistency of test program executions
An important means of validating the design of commercial-grade shared memory multiprocessors is to run a large number of pseudo-random test programs on them. However, when intent...
Chaiyasit Manovit, Sudheendra Hangal
139
Voted
HPCA
2006
IEEE
16 years 6 months ago
Efficient instruction schedulers for SMT processors
We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently propos...
Joseph J. Sharkey, Dmitry V. Ponomarev
HPCA
2006
IEEE
16 years 6 months ago
Exploiting parallelism and structure to accelerate the simulation of chip multi-processors
Simulation is an important means of evaluating new microarchitectures. Current trends toward chip multiprocessors (CMPs) try the ability of designers to develop efficient simulato...
David A. Penry, Daniel Fay, David Hodgdon, Ryan We...
HPCA
2006
IEEE
16 years 6 months ago
Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM
Measurements of an off-the-shelf DRAM chip confirm that different cells retain information for different amounts of time. This result extends to DRAM rows, or pages (retention tim...
Ravi K. Venkatesan, Stephen Herr, Eric Rotenberg
HPCA
2005
IEEE
16 years 6 months ago
Performance, Energy, and Thermal Considerations for SMT and CMP Architectures
Simultaneous multithreading (SMT) and chip multiprocessing (CMP) both allow a chip to achieve greater throughput, but their relative energy-efficiency and thermal properties are s...
Yingmin Li, David Brooks, Zhigang Hu, Kevin Skadro...
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