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    A novel wavelet transform based transient current analysis for fault detection and localization
    16 years 3 months ago
    A novel wavelet transform based transient current analysis for fault detection and localization
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    Swarup Bhunia, Kaushik Roy, Jaume Segura
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    Can BDDs compete with SAT solvers on bounded model checking?
    16 years 3 months ago
    Can BDDs compete with SAT solvers on bounded model checking?
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    Gianpiero Cabodi, Paolo Camurati, Stefano Quer
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    DAC
    2002
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    86views Computer Architecture» more  DAC 2002»
    S-Tree: a technique for buffered routing tree synthesis
    16 years 3 months ago
    S-Tree: a technique for buffered routing tree synthesis
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    Milos Hrkic, John Lillis
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    DAC
    2002
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    123views Computer Architecture» more  DAC 2002»
    Implementing asynchronous circuits using a conventional EDA tool-flow
    16 years 3 months ago
    Implementing asynchronous circuits using a conventional EDA tool-flow
    Download  www.bcim.lsbu.ac.uk
    Christos P. Sotiriou
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    127
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    2003
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    Timing optimization of FPGA placements by logic replication
    16 years 3 months ago
    Timing optimization of FPGA placements by logic replication
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    Giancarlo Beraudo, John Lillis
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