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ICCAD
2006
IEEE
96views Hardware» more  ICCAD 2006»
15 years 11 months ago
Loop pipelining for high-throughput stream computation using self-timed rings
We present a technique for increasing the throughput of stream processing architectures by removing the bottlenecks caused by loop structures. We implement loops as self-timed pip...
Gennette Gill, John Hansen, Montek Singh
FCCM
2005
IEEE
124views VLSI» more  FCCM 2005»
15 years 8 months ago
Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA
The CLA-EC is a model obtained by combining the concepts of cellular learning automata and evolutionary algorithms. The parallel structure of the CLA-EC makes it suitable for hard...
Arash Hariri, Reza Rastegar, Morteza Saheb Zamani,...
CCECE
2006
IEEE
15 years 9 months ago
Survey of Biological High Performance Computing: Algorithms, Implementations and Outlook Research
During recent years there has been an explosive growth of biological data coming from genome projects, proteomics, protein structure determination, and the rapid expansion in digi...
Nasreddine Hireche, J. M. Pierre Langlois, Gabriel...
ICCCN
2007
IEEE
15 years 9 months ago
Serial Sum-Product Architecture for Low-Density Parity-Check Codes
—A serial sum-product architecture for low-density parity-check (LDPC) codes is presented. In the proposed architecture, a standard bit node processing unit computes the bit to c...
Ruwan N. S. Ratnayake, Erich F. Haratsch, Gu-Yeon ...
RECONFIG
2008
IEEE
122views VLSI» more  RECONFIG 2008»
15 years 9 months ago
Using a CSP Based Programming Model for Reconfigurable Processor Arrays
The growing trend towards adoption of flexible and heterogeneous, parallel computing architectures has increased the challenges faced by the programming community. We propose a me...
Zain-ul-Abdin, Bertil Svensson