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ICSOC
2003
Springer
15 years 8 months ago
Reflective Architectures for Adaptive Information Systems
Andrea Maurino, Stefano Modafferi, Barbara Pernici
127
Voted
ASAP
2009
IEEE
95views Hardware» more  ASAP 2009»
15 years 8 months ago
A FPGA-based Parallel Architecture for Scalable High-Speed Packet Classification
Weirong Jiang, Viktor K. Prasanna
DAC
1989
ACM
15 years 7 months ago
Special Purpose Architecture for Accelerating Bitmap DRC
In this paper we propose algorithms for performing DRC on a bitmapped layout altd developspecial purpose architecture for its implementation. we Use window scan method, with flexib...
Narasimha B. Bhat, S. K. Nandy
98
Voted
APCSAC
2006
IEEE
15 years 9 months ago
Reliable Systolic Computing Through Redundancy
The systolic array paradigm has low communication demand because it does not use costly global communication and each processor communicates with few other processors. It is thus s...
Kunio Okuda, Siang Wun Song, Marcos Tatsuo Yamamot...