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DAC
2006
ACM
15 years 10 months ago
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
Yu Hu, Yan Lin, Lei He, Tim Tuan
DAC
2006
ACM
15 years 10 months ago
Exploring compromises among timing, power and temperature in three-dimensional integrated circuits
Three-dimensional integrated circuits (3DICs) have the potential to reduce interconnect lengths and improve digital system performance. However, heat removal is more difficult in ...
Hao Hua, Christopher Mineo, Kory Schoenfliess, Amb...
DAC
2006
ACM
15 years 10 months ago
HybDTM: a coordinated hardware-software approach for dynamic thermal management
With ever-increasing power density and cooling costs in modern high-performance systems, dynamic thermal management (DTM) has emerged as an effective technique for guaranteeing th...
Amit Kumar 0002, Li Shang, Li-Shiuan Peh, Niraj K....
DAC
2006
ACM
15 years 10 months ago
MARS-C: modeling and reduction of soft errors in combinational circuits
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we pre...
Natasa Miskov-Zivanov, Diana Marculescu
DAC
2006
ACM
15 years 10 months ago
Optimal cell flipping in placement and floorplanning
In a placed circuit, there are a lot of movable cells that can be flipped to further reduce the total wirelength, without affecting the original placement solution. We aim at solv...
Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N...
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