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CGO
2008
IEEE
15 years 4 months ago
Parallel-stage decoupled software pipelining
In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as the dominant design paradigm. For existing and ne...
Easwaran Raman, Guilherme Ottoni, Arun Raman, Matt...
CODES
2008
IEEE
15 years 4 months ago
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs
Modern embedded compute platforms increasingly contain both microprocessors and field-programmable gate arrays (FPGAs). The FPGAs may implement accelerators or other circuits to s...
David Sheldon, Frank Vahid
IEEEPACT
2008
IEEE
15 years 4 months ago
Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor
Moore’s Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneo...
Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aa...
IROS
2008
IEEE
137views Robotics» more  IROS 2008»
15 years 4 months ago
Universal web interfaces for robot control frameworks
— Developers and end-users have to interface robotic systems for control and feedback. Such systems are typically co-engineered with their graphical user interfaces. In the past,...
Jan Koch, Max Reichardt, Karsten Berns
ISCA
2008
IEEE
142views Hardware» more  ISCA 2008»
15 years 4 months ago
Improving NAND Flash Based Disk Caches
Flash is a widely used storage device that provides high density and low power, appealing properties for general purpose computing. Today, its usual application is in portable spe...
Taeho Kgil, David Roberts, Trevor N. Mudge
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