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DAC
1993
ACM
15 years 8 months ago
A Negative Reinforcement Method for PGA Routing
We present an efficient and effective method for the detailed routing of symmetrical or sea-of-gates FPGA architectures. Instead of breaking the problem into 2-terminal net collec...
Forbes D. Lewis, Wang Chia-Chi Pong
IPPS
1998
IEEE
15 years 8 months ago
PACE: Processor Architectures for Circuit Emulation
We describe a family of reconfigurable parallel architectures for logic emulation. They are supposed to be applicable like conventional FPGAs, while covering a larger range of circ...
Reiner Kolla, Oliver Springauf
IPPS
2008
IEEE
15 years 10 months ago
DC-SIMD : Dynamic communication for SIMD processors
SIMD (single instruction multiple data)-type processors have been found very efficient in image processing applications, because their repetitive structure is able to exploit the...
Raymond Frijns, Hamed Fatemi, Bart Mesman, Henk Co...
RTCSA
2005
IEEE
15 years 9 months ago
Research Issues in the Development of Context-Aware Middleware Architectures
Context-aware middleware encompasses uniform ions and reliable services for common operations, supports for most of the tasks involved in dealing with context, and thus simplifyin...
Hung Quoc Ngo, Anjum Shehzad, Kim Anh Pham Ngoc, S...
IPPS
2010
IEEE
15 years 1 months ago
Tile QR factorization with parallel panel processing for multicore architectures
To exploit the potential of multicore architectures, recent dense linear algebra libraries have used tile algorithms, which consist in scheduling a Directed Acyclic Graph (DAG) of...
Bilel Hadri, Hatem Ltaief, Emmanuel Agullo, Jack D...