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DSN
2008
IEEE
15 years 11 months ago
A fault-tolerant directory-based cache coherence protocol for CMP architectures
Current technology trends of increased scale of integration are pushing CMOS technology into the deepsubmicron domain, enabling the creation of chips with a significantly greater...
Ricardo Fernández Pascual, José M. G...
DATE
2006
IEEE
88views Hardware» more  DATE 2006»
15 years 11 months ago
Temporal partitioning for image processing based on time-space complexity in reconfigurable architectures
Temporal partitioning techniques are useful to implement large and complex applications, which can be split into partitions in FPGA devices. In order to minimize resources, each o...
Paulo Sérgio B. do Nascimento, Manoel Euseb...
CLUSTER
2003
IEEE
15 years 10 months ago
Implications of a PIM Architectural Model for MPI
Memory may be the only system component that is more commoditized than a microprocessor. To simultaneously exploit this and address the impending memory wall, processing in memory...
Arun Rodrigues, Richard C. Murphy, Peter M. Kogge,...
DSN
2000
IEEE
15 years 9 months ago
A Low Latency, Loss Tolerant Architecture and Protocol for Wide Area Group Communication
Group communication systems are proven tools upon which to build fault-tolerant systems. As the demands for fault-tolerance increase and more applications require reliable distrib...
Yair Amir, Claudiu Danilov, Jonathan Robert Stanto...
IPPS
1998
IEEE
15 years 9 months ago
Hyper Butterfly Network: A Scalable Optimally Fault Tolerant Architecture
Boundeddegreenetworks like deBruijn graphsor wrapped butterfly networks are very important from VLSI implementation point of view as well as for applications where the computing n...
Wei Shi, Pradip K. Srimani