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FPL
2003
Springer
146views Hardware» more  FPL 2003»
15 years 10 months ago
Domain-Specific Reconfigurable Array for Distributed Arithmetic
Distributed Arithmetic techniques are widely used to implement Sum-of-Products computations such as calculations found in multimedia applications like FIR filtering and Discrete Co...
Sami Khawam, Tughrul Arslan, Fred Westall
IEEEPACT
2009
IEEE
15 years 11 months ago
Flextream: Adaptive Compilation of Streaming Applications for Heterogeneous Architectures
Increasing demand for performance and efficiency has driven the computer industry toward multicore systems. These systems have become the industry standard in almost all segments...
Amir Hormati, Yoonseo Choi, Manjunath Kudlur, Rodr...
APCSAC
2003
IEEE
15 years 8 months ago
Simultaneous MultiStreaming for Complexity-Effective VLIW Architectures
Very Long Instruction Word (VLIW) architectures exploit instruction level parallelism (ILP) with the help of the compiler to achieve higher instruction throughput with minimal hard...
Pradeep Rao, S. K. Nandy, M. N. V. Satya Kiran
JSSPP
1995
Springer
15 years 8 months ago
Time Space Sharing Scheduling and Architectural Support
In this paper, we describe a new job scheduling class, called \Time Space Sharing Scheduling" (TSSS) for dynamically partitionable parallel machines. As an instance of TSSS, ...
Atsushi Hori, Takashi Yokota, Yutaka Ishikawa, Shu...
IPPS
2006
IEEE
15 years 11 months ago
An optimal architecture for a DDC
Digital Down Conversion (DDC) is an algorithm, used to lower the amount of samples per second by selecting a limited frequency band out of a stream of samples. A possible DDC algo...
Tjerk Bijlsma, Pascal T. Wolkotte, Gerard J. M. Sm...