Abstract—In this paper we focus on optimizing the performance in a cluster of Simultaneous Multithreading (SMT) processors connected with a commodity interconnect (e.g. Gbit Ethe...
Georgios I. Goumas, Nikos Anastopoulos, Nectarios ...
This paper proposes a comprehensive modeling architecture for workloads on parallel computers using Markov chains in combination with state dependent empirical distribution functi...
In this paper, we investigate the power implications of tile size selection for tile-based processors. We refer to this investigation as a tile granularity study. This is accompli...
John Oliver, Ravishankar Rao, Michael Brown, Jenni...
ArchiTRIO is a formal language, which complements UML 2.0 concepts with a formal, logic-based notation that allows users to state system-wide properties, both static and dynamic, ...
Conventional wisdom has held that routing protocols cannot achieve both scalability and high availability. Despite scaling relatively well, today's Internet routing system do...
Yaping Zhu, Andy C. Bavier, Nick Feamster, Sampath...