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SBACPAD
2005
IEEE
139views Hardware» more  SBACPAD 2005»
15 years 11 months ago
Chained In-Order/Out-of-Order DoubleCore Architecture
Complexity is one of the most important problems facing microarchitects. It is exacerbated by the application of optimizations, by scaling to higher issue widths and, in general, ...
Miquel Pericàs, Adrián Cristal, Rube...
CF
2005
ACM
15 years 8 months ago
Dynamic loop pipelining in data-driven architectures
Data-driven array architectures seem to be important alternatives for coarse-grained reconfigurable computing platforms. Their use has provided performance improvements over micro...
João M. P. Cardoso
CCR
2010
132views more  CCR 2010»
15 years 3 months ago
Scafida: a scale-free network inspired data center architecture
Data centers have a crucial role in current Internet architecture supporting content-centric networking. State-of-theart data centers have different architectures like fat-tree [1...
László Gyarmati, Tuan Anh Trinh
IEEEPACT
2002
IEEE
15 years 11 months ago
Optimizing Loop Performance for Clustered VLIW Architectures
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
Yi Qian, Steve Carr, Philip H. Sweany
IAJIT
2010
107views more  IAJIT 2010»
15 years 4 months ago
Low Latency, High Throughput, and Less Complex VLSI Architecture for 2D-DFT
: This paper proposes a pipelined, systolic architecture for two- dimensional discrete Fourier transform computation which is highly concurrent. The architecture consists of two, o...
Sohil Shah, Preethi Venkatesan, Deepa Sundar, Muni...