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CICC
2011
106views more  CICC 2011»
14 years 6 months ago
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the limited scalability of...
Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D....
ANCS
2006
ACM
16 years 1 days ago
A practical fast parallel routing architecture for Clos networks
Clos networks are an important class of switching networks due to their modular structure and much lower cost compared with crossbars. For routing I/O permutations of Clos network...
Si-Qing Zheng, Ashwin Gumaste, Enyue Lu
SAMOS
2009
Springer
15 years 10 months ago
CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey
The demands for high quality, real-time performance and multi-format video support in consumer multimedia products are ever increasing. In particular, the future multimedia systems...
Yahya Jan, Lech Józwiak
CIA
2008
Springer
15 years 8 months ago
Towards an Open Negotiation Architecture for Heterogeneous Agents
This paper presents the design of an open architecture for heterogeneous negotiating agents. Both the system level architecture as well as the architecture for negotiating agents a...
Koen V. Hindriks, Catholijn M. Jonker, Dmytro Tykh...
VLSID
2001
IEEE
118views VLSI» more  VLSID 2001»
16 years 6 months ago
Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language
Memory represents a major bottleneck in modern embedded systems. Traditionally, memory organizationsfor programmable systems assumed a fixed cache hierarchy. Withthe wideningproce...
Prabhat Mishra, Peter Grun, Nikil D. Dutt, Alexand...