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ARITH
1999
IEEE
15 years 10 months ago
Reduced Latency IEEE Floating-Point Standard Adder Architectures
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...
Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, C...
IWAN
1999
Springer
15 years 10 months ago
ANMAC: An Architectural Framework for Network Management and Control using Active Networks
In this paper, we propose a new framework called Active Network Management and Control (ANMAC) for the management and control of high speed networks. The software architecture in A...
Samphel Norden, Kenneth F. Wong
IEEEPACT
1998
IEEE
15 years 10 months ago
Optical versus Electronic Bus for Address-Transactions in Future SMP Architectures
The fast evolution of processor performance necessitates a permanent evolution of all the multiprocessor components, even for small to medium-scale symmetric multiprocessors (SMP)...
Wissam Hlayhel, Daniel Litaize, Laurent Fesquet, J...
ISCA
1998
IEEE
126views Hardware» more  ISCA 1998»
15 years 10 months ago
Switcherland: A QoS Communication Architecture for Workstation Clusters
Computer systems have become powerful enough to process continuous data streams such as video or animated graphics. While processing power and communication bandwidth of today...
Hans Eberle, Erwin Oertli
ISPAN
1997
IEEE
15 years 10 months ago
CASS: an efficient task management system for distributed memory architectures
The thesis of this research is that the task of exposing the parallelism in a given application should be left to the algorithm designer, who has intimate knowledge of the applica...
Jing-Chiou Liou, Michael A. Palis