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IPPS
1994
IEEE
15 years 10 months ago
Parallel Evaluation of a Parallel Architecture by Means of Calibrated Emulation
A parallel transputer-based emulator has been developed to evaluate the DDM--ahighlyparallel virtual shared memory architecture. The emulator provides performance results of a har...
Henk L. Muller, Paul W. A. Stallard, David H. D. W...
HVC
2007
Springer
153views Hardware» more  HVC 2007»
15 years 10 months ago
On the Architecture of System Verification Environments
Implementations of computer systems comprise many layers and employ a variety of programming languages. Building such systems requires support of an often complex, accompanying too...
Mark A. Hillebrand, Wolfgang J. Paul
AINA
2006
IEEE
15 years 10 months ago
EC: an edge-based architecture against DDoS attacks and malware spread
The ability to limit unsolicited traffic in the Internet is important to defy DDoS attacks and to contain the spread of worms and viruses. The concept of capabilities, which requir...
Roger Karrer
FPL
2006
Springer
140views Hardware» more  FPL 2006»
15 years 10 months ago
Architectural Modifications to Improve Floating-Point Unit Efficiency in FPGAs
FPGAs have reached densities that can implement floatingpoint applications, but floating-point operations still require a large amount of FPGA resources. One major component of IE...
Michael J. Beauchamp, Scott Hauck, Keith D. Underw...
IPPS
1998
IEEE
15 years 10 months ago
Comparing the Optimal Performance of Different MIMD Multiprocessor Architectures
We compare the performance of systems consisting of one large cluster containing q processors with systems where processors are grouped into k clusters containing u processors eac...
Lars Lundberg, Håkan Lennerstad