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DAC
1999
ACM
15 years 4 months ago
Circuit Complexity Reduction for Symbolic Analysis of Analog Integrated Circuits
This paper presents a method to reduce the complexity of a linear or linearized (small-signal) analog circuit. The reduction technique, based on quality-error ranking, can be used...
Walter Daems, Georges G. E. Gielen, Willy M. C. Sa...
DAC
2006
ACM
16 years 20 days ago
A real time budgeting method for module-level-pipelined bus based system using bus scenarios
In designing bus based systems with parallel and pipelined architecture, it is important to derive a real time budget (a specified execution time limit) for each task of a bus bas...
Tadaaki Tanimoto, Seiji Yamaguchi, Akio Nakata, Te...
CAD
2005
Springer
14 years 11 months ago
Creation of a unit block library of architectures for use in assembled scaffold engineering
Guided tissue regeneration is gaining importance in the field of orthopaedic tissue engineering as need and technology permits the development of site-specific engineering approac...
M. A. Wettergreen, B. S. Bucklen, Binil Starly, E....
DAC
2007
ACM
16 years 21 days ago
Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction
The ability to account for the growing impacts of multiple process variations in modern technologies is becoming an integral part of nanometer VLSI design. Under the context of ti...
Zhuo Feng, Peng Li, Yaping Zhan
DAC
2003
ACM
16 years 20 days ago
Analog and RF circuit macromodels for system-level analysis
Design and validation of mixed-signal integrated systems require evel model abstractions. Generalized Volterra series based models have been successfully applied for analog and RF...
Xin Li, Peng Li, Yang Xu, Lawrence T. Pileggi