This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more tim...
Young-Il Kim, Woo-Seung Yang, Young-Su Kwon, Chong...
We study diagnosis of segments on speedpaths that fail the timing constraint at the post-silicon stage due to manufacturing variations. We propose a formal procedure that is appli...
The transition to multicore architectures has dramatically underscored the necessity for parallelism in software. In particular, while new gaming consoles are by and large multicor...
Micah J. Best, Alexandra Fedorova, Ryan Dickie, An...
Input Buffered Switches with Virtual Output Queues(VOQ) design to avoid Head-Of-Line problems, is a primary design of switches that can be scalable to very high speeds. However, t...
This paper presents a new algorithm for exact estimation of the minimum memory size required by programs dealing with array computations. Memory size is an important factor a ecti...