Sciweavers

397 search results - page 63 / 80
» Computer aided architectural design: Wayfinding complexity a...
Sort
View
125
Voted
DAC
2009
ACM
15 years 10 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
DATE
2009
IEEE
122views Hardware» more  DATE 2009»
15 years 10 months ago
Model-based synthesis and optimization of static multi-rate image processing algorithms
Abstract—High computational effort in modern image processing applications like medical imaging or high-resolution video processing often demands for massively parallel special p...
Joachim Keinert, Hritam Dutta, Frank Hannig, Chris...
DAC
2010
ACM
15 years 4 months ago
Detecting tangled logic structures in VLSI netlists
This work proposes a new problem of identifying large and tangled logic structures in a synthesized netlist. Large groups of cells that are highly interconnected to each other can...
Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li...
DAC
2007
ACM
16 years 4 months ago
An Effective Guidance Strategy for Abstraction-Guided Simulation
tive Guidance Strategy for Abstraction-Guided Simulation Flavio M. De Paula Alan J. Hu Department of Computer Science, University of British Columbia, {depaulfm, ajh}@cs.ubc.ca D...
Flavio M. de Paula, Alan J. Hu
CHARME
2003
Springer
196views Hardware» more  CHARME 2003»
15 years 8 months ago
Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT
We present a non-operational approach to specifying and analyzing shared memory consistency models. The method uses higher order logic to capture a complete set of ordering constra...
Yue Yang, Ganesh Gopalakrishnan, Gary Lindstrom, K...