8008 search results - page 22 / 1602 » Computer-Aided Language Processing |
DAC
2005
ACM
15 years 10 months ago
2005
ACM
As the process technology enters the nanometer era, reliability has become a major concern in the design and manufacturing of VLSI circuits. In this paper we focus on one reliabil...
47
Voted
DAC
2006
ACM
15 years 10 months ago
2006
ACM
Antenna effect may damage gate oxides during plasma-based fabrication process. The antenna ratio of total exposed antenna area to total gate oxide area is directly related to the ...
ISPD
2010
ACM
15 years 4 months ago
2010
ACM
Double Patterning Lithography (DPL) is one of the few hopeful candidate solutions for the lithography for CMOS process beyond 45nm. DPL assigns the patterns less than a certain di...
74
Voted
GLVLSI
2009
IEEE
15 years 4 months ago
2009
IEEE
In the context of formal verification Bounded Model Checking (BMC) has shown to be very powerful for large industrial designs. BMC is used to check whether a circuit satisfies a...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
The problem of diagnosis – or locating the source of an error or fault – occurs in several areas of Computer Aided Design, such as dynamic verification, property checking, eq...