Conventional physical design flow separates the design of power network and signal network. Such a separated approach results in slow design convergence for wire-limited deep sub-...
This paper presents the influence of the loop nest splitting source code optimization on the worst-case execution time (WCET). Loop nest splitting minimizes the number of executed...
: Six DOF offset sensing between two plates is important for automatic docking mechanisms. This paper presents an easy and inexpensive implementation of such a system using four co...
We present a model for the parallel performance of algorithms that consist of concurrent, two-dimensional wavefronts implemented in a message passing environment. The model combine...
Adolfy Hoisie, Olaf M. Lubeck, Harvey J. Wasserman
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...