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DATE
2004
IEEE
116views Hardware» more  DATE 2004»
15 years 6 months ago
Full-Chip Multilevel Routing for Power and Signal Integrity
Conventional physical design flow separates the design of power network and signal network. Such a separated approach results in slow design convergence for wire-limited deep sub-...
Jinjun Xiong, Lei He
ESTIMEDIA
2006
Springer
15 years 6 months ago
Loop Nest Splitting for WCET-Optimization and Predictability Improvement
This paper presents the influence of the loop nest splitting source code optimization on the worst-case execution time (WCET). Loop nest splitting minimizes the number of executed...
Heiko Falk, Martin Schwarzer
ISER
2000
Springer
74views Robotics» more  ISER 2000»
15 years 6 months ago
Six Degree of Freedom Sensing for Docking Using IR LED Emitters and Receivers
: Six DOF offset sensing between two plates is important for automatic docking mechanisms. This paper presents an easy and inexpensive implementation of such a system using four co...
Kimon Roufas, Ying Zhang, David Duff, Mark Yim
WAN
1998
Springer
15 years 6 months ago
Performance Analysis of Wavefront Algorithms on Very-Large Scale Distributed Systems
We present a model for the parallel performance of algorithms that consist of concurrent, two-dimensional wavefronts implemented in a message passing environment. The model combine...
Adolfy Hoisie, Olaf M. Lubeck, Harvey J. Wasserman
124
Voted
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
15 years 6 months ago
Layout Driven Logic Restructuring/Decomposition
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
Massoud Pedram, Narasimha B. Bhat