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VLSID
2002
IEEE
78views VLSI» more  VLSID 2002»
16 years 6 months ago
Optimization of Test Accesses with a Combined BIST and External Test Scheme
External pins for test are precious hardware resources because this number is strongly restricted. Cores are tested via test access mechanisms (TAMs) such as a test bus architectu...
Makoto Sugihara, Hiroto Yasuura
VLSID
2001
IEEE
200views VLSI» more  VLSID 2001»
16 years 6 months ago
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures
The emergence of several communication architectures for System-on-Chips provides designers with a variety of design alternatives. In addition, the need to customize the system ar...
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
POPL
2008
ACM
16 years 6 months ago
High-level small-step operational semantics for transactions
Software transactions have received significant attention as a way to simplify shared-memory concurrent programming, but insufficient focus has been given to the precise meaning o...
Katherine F. Moore, Dan Grossman
POPL
2007
ACM
16 years 6 months ago
Specialization of CML message-passing primitives
Concurrent ML (CML) is a statically-typed higher-order concurrent language that is embedded in Standard ML. Its most notable feature is its support for first-class synchronous ope...
John H. Reppy, Yingqi Xiao
CADE
2006
Springer
16 years 6 months ago
CEL - A Polynomial-Time Reasoner for Life Science Ontologies
CEL (Classifier for EL) is a reasoner for the small description logic EL+ which can be used to compute the subsumption hierarchy induced by EL+ ontologies. The most distinguishing ...
Franz Baader, Carsten Lutz, Boontawee Suntisrivara...
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