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EURODAC
1994
IEEE
127views VHDL» more  EURODAC 1994»
15 years 8 months ago
Optimal equivalent circuits for interconnect delay calculations using moments
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...
Sudhakar Muddu, Andrew B. Kahng
143
Voted
ICDE
1993
IEEE
158views Database» more  ICDE 1993»
15 years 8 months ago
Unification of Temporal Data Models
To add time su port to the relational model, both first normal form (fNF and non-INF appmches have maining within 1NF when time support is added may introduce data redundancy. The...
Christian S. Jensen, Michael D. Soo, Richard T. Sn...
ICCAD
1994
IEEE
117views Hardware» more  ICCAD 1994»
15 years 8 months ago
Optimization of critical paths in circuits with level-sensitive latches
A simple extension of the critical path method is presented which allows more accurate optimization of circuits with level-sensitive latches. The extended formulation provides a s...
Timothy M. Burks, Karem A. Sakallah
ICCAD
1994
IEEE
131views Hardware» more  ICCAD 1994»
15 years 8 months ago
Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
Hannah Honghua Yang, D. F. Wong
INFOCOM
1993
IEEE
15 years 8 months ago
A Generalized Processor Sharing Approach to Flow Control in Integrated Services Networks: The Multiple Node Case
Worst-casebounds on delay and backlog are derived for leaky bucket constrained sessions in arbitrary topology networks of Generalized Processor Sharing (GPS) 10] servers. The inhe...
Abhay K. Parekh, Robert G. Gallager
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