In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...
To add time su port to the relational model, both first normal form (fNF and non-INF appmches have maining within 1NF when time support is added may introduce data redundancy. The...
Christian S. Jensen, Michael D. Soo, Richard T. Sn...
A simple extension of the critical path method is presented which allows more accurate optimization of circuits with level-sensitive latches. The extended formulation provides a s...
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
Worst-casebounds on delay and backlog are derived for leaky bucket constrained sessions in arbitrary topology networks of Generalized Processor Sharing (GPS) 10] servers. The inhe...