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ISCAS
2005
IEEE
133views Hardware» more  ISCAS 2005»
15 years 10 months ago
Minimal activity mixed-signal VLSI architecture for real-time linear transforms in video
Abstract— The mixed-signal processor performs digital vectormatrix multiplication using internally analog fine-grain parallel computing. The three-transistor CID/DRAM unit cell ...
Rafal Karakiewicz, Roman Genov
140
Voted
IPPS
2000
IEEE
15 years 9 months ago
Replicating the Contents of a WWW Multimedia Repository to Minimize Download Time
Dynamic replication algorithms aim at allocating, migrating and deleting copies of an object over various Internet hosts, according to the access patterns exhibited online, so as ...
Thanasis Loukopoulos, Ishfaq Ahmad
DAC
1999
ACM
15 years 8 months ago
Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing
We present a new approach for estimation and optimization of the average stand-by power dissipation in large MOS digital circuits. To overcome the complexity of state dependence i...
Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, J...
ICNP
1998
IEEE
15 years 8 months ago
A Lossless, Minimal Latency Protocol for Gigabit ATM Networks
Advances in ber-optic and VLSI technology have led to the emergence of very high-speed networks based on Asynchronous Transfer Mode ATM. The time required to transmit the data int...
Michael D. Santos, P. M. Melliar-Smith, Louise E. ...
151
Voted
DAC
2007
ACM
15 years 8 months ago
Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits
Mixed Vt has been widely used to control leakage without affecting circuit performance. However, current approaches target the combinational circuits even though sequential elemen...
Jun Seomun, Jaehyun Kim, Youngsoo Shin