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ECBS
1996
IEEE
155views Hardware» more  ECBS 1996»
15 years 10 months ago
Model-Integrated Program Synthesis Environment
In this paper, it is shown that, through the use of Model-Integrated Program Synthesis MIPS, parallel real-time implementations of image processing data ows can be synthesized fro...
Janos Sztipanovits, Gabor Karsai, Hubertus Franke
133
Voted
ECP
1997
Springer
103views Robotics» more  ECP 1997»
15 years 10 months ago
Plan-Refinement Strategies and Search-Space Size
During the planning process, a planner may have many options for refinements to perform on the plan being developed. The planner’s efficiency depends on how it chooses which ref...
Reiko Tsuneto, Dana S. Nau, James A. Hendler
156
Voted
DAC
2010
ACM
15 years 10 months ago
TSV stress aware timing analysis with applications to 3D-IC layout optimization
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...
Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee,...
AFRIGRAPH
2010
ACM
15 years 10 months ago
Visualization of solution sets from automated docking of molecular structures
Aligning structures, often referred to as docking or registration, is frequently required in fields such as computer science, robotics and structural biology. The task of alignin...
Johannes Jansen van Vuuren, Michelle Kuttel, James...
177
Voted
CGO
2004
IEEE
15 years 10 months ago
Custom Data Layout for Memory Parallelism
In this paper, we describe a generalized approach to deriving a custom data layout in multiple memory banks for array-based computations, to facilitate high-bandwidth parallel mem...
Byoungro So, Mary W. Hall, Heidi E. Ziegler
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