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» Computing a Center-Transversal Line
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81
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DAC
1998
ACM
16 years 3 days ago
Layout Techniques for Minimizing On-Chip Interconnect Self Inductance
Because magnetic e ects have a much longer spatial range than electrostatic e ects, an interconnect line with large inductance will be sensitive to distant variations in interconn...
Yehia Massoud, Steve S. Majors, Tareq Bustami, Jac...
DAC
2001
ACM
16 years 3 days ago
Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs
Non-uniform temperature profiles along global interconnect lines in high-performance ICs can significantly impact the performance of these lines. This paper presents a detailed an...
Amir H. Ajami, Kaustav Banerjee, Massoud Pedram, L...
ETFA
2006
IEEE
15 years 5 months ago
Implementation of an Internet-controlled system under variable delays
Abstract— This work deals with the control and the observation of a remote system using Internet as a communication line. The process consists in a Slave part S, with poor comput...
Alexandre Seuret, M. Termens-Ballester, A. Toguyen...
76
Voted
GLOBECOM
2006
IEEE
15 years 5 months ago
Band-Preference Dynamic Spectrum Management in a DSL Environment
— This paper introduces an algorithm for spectrum management for digital subscriber line (DSL) systems based on band preference. The proposed method influences the usage of spec...
Wooyul Lee, Youngjae Kim, Mark H. Brady, John M. C...
HAPTICS
2005
IEEE
15 years 4 months ago
Bi-Level and Anti-Aliased Rendering Methods for a Low-Resolution 2D Vibrotactile Array
We investigate rendering methods for 2D tactile arrays. We present four rendering methods, two of which are anti-aliased methods to improve display quality and smoothness. We desc...
Christoph W. Borst, Alp V. Asutay