2255 search results - page 182 / 451 » Computing a Center-Transversal Line |
131
Voted
HPCA
2009
IEEE
16 years 4 months ago
2009
IEEE
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...
191
Voted
HPCA
2004
IEEE
16 years 3 months ago
2004
IEEE
Recent research suggests that there are large variations in a cache's spatial usage, both within and across programs. Unfortunately, conventional caches typically employ fixe...
108
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CHI
2004
ACM
16 years 3 months ago
2004
ACM
This poster describes an integrated set of stories and story-based activities that we have used in product development in IBM Software Group's Lotus product organizations. We...
128
Voted
DAC
2009
ACM
15 years 10 months ago
2009
ACM
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
126
Voted
IPPS
2005
IEEE
15 years 9 months ago
2005
IEEE
As technological process shrinks and clock rate increases, instruction caches can no longer be accessed in one cycle. Alternatives are implementing smaller caches (with higher mis...