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» Computing bounds for fault tolerance using formal techniques
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ISLPED
2009
ACM
132views Hardware» more  ISLPED 2009»
15 years 4 months ago
Enabling ultra low voltage system operation by tolerating on-chip cache failures
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
81
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GI
2004
Springer
15 years 3 months ago
Reliability study of an embedded operating system for industrial applications
: Critical industrial applications or fault tolerant applications need for operating systems (OS) which guarantee a correct and safe behaviour despite the appearance of errors. In ...
Juan Pardo, José Carlos Campelo, Juan Jos&e...
SEDE
2007
14 years 11 months ago
Case study: A tool centric approach for fault avoidance in microchip designs
— Achieving reliability in fault tolerant systems requires both avoidance and redundancy. This study focuses on avoidance as it pertains to the design of microchips. The lifecycl...
Clemente Izurieta
ET
2010
89views more  ET 2010»
14 years 8 months ago
On the Duality of Probing and Fault Attacks
In this work we investigate the problem of simultaneous privacy and integrity protection in cryptographic circuits. We consider a white-box scenario with a powerful, yet limited at...
Berndt M. Gammel, Stefan Mangard
SPAA
2010
ACM
15 years 2 months ago
Securing every bit: authenticated broadcast in radio networks
This paper studies non-cryptographic authenticated broadcast in radio networks subject to malicious failures. We introduce two protocols that address this problem. The first, Nei...
Dan Alistarh, Seth Gilbert, Rachid Guerraoui, Zark...