242 search results - page 25 / 49 » Computing bounds for fault tolerance using formal techniques |
SAC
2006
ACM
15 years 3 months ago
2006
ACM
: In chip design, one of the main objectives is to decrease its clock cycle; however, the existing approaches to timing analysis under uncertainty are based on fundamentally restri...
101
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DAC
2003
ACM
15 years 10 months ago
2003
ACM
Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems bei...
DSVIS
2005
Springer
15 years 3 months ago
2005
Springer
The calculus outlined in this paper provides a formal architectural framework for describing and reasoning about the properties of multi-user and mobile distributed interactive sys...
FM
2003
Springer
15 years 2 months ago
2003
Springer
Safety is increasingly important for software based, critical systems. Fault tree analysis (FTA) is a safety technique from engineering, developed for analyzing and assessing syste...
112
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ADHOCNOW
2007
Springer
15 years 3 months ago
2007
Springer
The increased use of ubiquitous computing devices is resulting in networks that are highly mobile, well connected and growing in processing and storage capabilities. The nature of ...