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ISCAS
2007
IEEE
161views Hardware» more  ISCAS 2007»
15 years 11 months ago
Hardware Architecture of a Parallel Pattern Matching Engine
Abstract— Several network security and QoS applications require detecting multiple string matches in the packet payload by comparing it against predefined pattern set. This proc...
Meeta Yadav, Ashwini Venkatachaliah, Paul D. Franz...
ICIP
2003
IEEE
16 years 6 months ago
Parallel-pipelined architecture for 2-D ICT VLSI implementation
The Integer Cosine Transform (ICT) has been shown to be an alternative to the DCT for image processing. This paper presents a parallel-pipelined architecture of an 8x8 ICT(10, 9, ...
Juan A. Michell, Gustavo A. Ruiz, Angel M. Buron
ICIP
1999
IEEE
16 years 6 months ago
Simplified Segmentation for Compound Image Compression
There are three basic segmentation schemes for compound image compression: object-based, layer-based, and block-based. This work discusses the relative advantages of each scheme a...
Amir Said, Alexander Drukarev
SASP
2008
IEEE
153views Hardware» more  SASP 2008»
15 years 11 months ago
TRaX: A Multi-Threaded Architecture for Real-Time Ray Tracing
Ray tracing is a technique used for generating highly realistic computer graphics images. In this paper, we explore the design of a simple but extremely parallel, multi-threaded, ...
Josef B. Spjut, Solomon Boulos, Daniel Kopta, Erik...
125
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IJCNN
2007
IEEE
15 years 11 months ago
FEBAM: A Feature-Extracting Bidirectional Associative Memory
—In this paper, a new model that can ultimately create its own set of perceptual features is proposed. Using a bidirectional associative memory (BAM)-inspired architecture, the r...
Sylvain Chartier, Gyslain Giguère, Patrice ...