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DAC
1997
ACM
15 years 3 months ago
Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets
The paper presents an algorithm to determine the close-tosmallest possible data buffer sizes for arbitrary synchronous data flow (SDF) applications, such that we can guarantee the...
Marleen Adé, Rudy Lauwereins, J. A. Peperst...
SBACPAD
2003
IEEE
137views Hardware» more  SBACPAD 2003»
15 years 5 months ago
Exploring Memory Hierarchy with ArchC
This paper presents the cache configuration exploration of a programmable system, in order to find the best matching between the architecture and a given application. Here, prog...
Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Aze...
EGITALY
2006
15 years 1 months ago
A Survey of Digital Mosaic Techniques
Art often provides valuable hints for technological innovations especially in the field of Image Processing and Computer Graphics. In this paper we survey in an unified framework ...
Sebastiano Battiato, Gianpiero di Blasi, Giovanni ...
SASP
2009
IEEE
222views Hardware» more  SASP 2009»
15 years 6 months ago
A memory optimization technique for software-managed scratchpad memory in GPUs
—With the appearance of massively parallel and inexpensive platforms such as the G80 generation of NVIDIA GPUs, more real-life applications will be designed or ported to these pl...
Maryam Moazeni, Alex A. T. Bui, Majid Sarrafzadeh
FPGA
2001
ACM
152views FPGA» more  FPGA 2001»
15 years 4 months ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
Jörg Ritter, Paul Molitor