Sciweavers

8669 search results - page 1509 / 1734
» Computing matrix representations
Sort
View
DAC
2008
ACM
16 years 4 months ago
Automatic synthesis of clock gating logic with controlled netlist perturbation
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...
Aaron P. Hurst
DAC
2002
ACM
16 years 4 months ago
Model order reduction for strictly passive and causal distributed systems
This paper presents a class of algorithms suitable for model reduction of distributed systems. Distributed systems are not suitable for treatment by standard model-reduction algor...
Luca Daniel, Joel R. Phillips
DAC
2002
ACM
16 years 4 months ago
Timed compiled-code simulation of embedded software for performance analysis of SOC design
In this paper, a new timing generation method is proposed for the performance analysis of embedded software. The time stamp generation of I/O accesses is crucial to performance es...
Jong-Yeol Lee, In-Cheol Park
DAC
2003
ACM
16 years 4 months ago
Data communication estimation and reduction for reconfigurable systems
Widespread adoption of reconfigurable devices requires system level synthesis techniques to take an application written in a high level language and map it to the reconfigurable d...
Adam Kaplan, Philip Brisk, Ryan Kastner
DAC
2003
ACM
16 years 4 months ago
A hybrid SAT-based decision procedure for separation logic with uninterpreted functions
SAT-based decision procedures for quantifier-free fragments of firstorder logic have proved to be useful in formal verification. These decision procedures are either based on enco...
Sanjit A. Seshia, Shuvendu K. Lahiri, Randal E. Br...
« Prev « First page 1509 / 1734 Last » Next »