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ARCS
2009
Springer
15 years 10 months ago
Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
Joseph Gebis, Leonid Oliker, John Shalf, Samuel Wi...
123
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TCC
2010
Springer
188views Cryptology» more  TCC 2010»
15 years 10 months ago
Founding Cryptography on Tamper-Proof Hardware Tokens
A number of works have investigated using tamper-proof hardware tokens as tools to achieve a variety of cryptographic tasks. In particular, Goldreich and Ostrovsky considered the ...
Vipul Goyal, Yuval Ishai, Amit Sahai, Ramarathnam ...
237
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POPL
2006
ACM
16 years 4 months ago
A hierarchical model of data locality
In POPL 2002, Petrank and Rawitz showed a universal result-finding optimal data placement is not only NP-hard but also impossible to approximate within a constant factor if P = NP...
Chengliang Zhang, Chen Ding, Mitsunori Ogihara, Yu...
96
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ASAP
2007
IEEE
136views Hardware» more  ASAP 2007»
15 years 10 months ago
0/1 Knapsack on Hardware: A Complete Solution
We present a memory efficient, practical, systolic, parallel architecture for the complete 0/1 knapsack dynamic programming problem, including backtracking. This problem was inte...
K. Nibbelink, S. Rajopadhye, R. McConnell
130
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DCOSS
2006
Springer
15 years 7 months ago
Y-Threads: Supporting Concurrency in Wireless Sensor Networks
Abstract. Resource constrained systems often are programmed using an eventbased model. Many applications do not lend themselves well to an event-based approach, but preemptive mult...
Christopher Nitta, Raju Pandey, Yann Ramin