4586 search results - page 764 / 918 » Computing stable models in parallel |
112
Voted
IEEEPACT
2005
IEEE
15 years 9 months ago
2005
IEEE
In this paper we compare the performance of area equivalent small, medium, and large-scale multithreaded chip multiprocessors (CMTs) using throughput-oriented applications. We use...
105
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CLUSTER
2009
IEEE
15 years 8 months ago
2009
IEEE
—Achieving high-performance message passing on top of generic ETHERNET hardware suffers from the NIC interruptdriven model where coalescing is usually involved. We present an in-...
134
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SIGOPS
2008
15 years 3 months ago
2008
This paper presents PipesFS, an I/O architecture for Linux 2.6 that increases I/O throughput and adds support for heterogeneous parallel processors by (1) collapsing many I/O inte...
113
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IEEECIT
2010
IEEE
15 years 2 months ago
2010
IEEE
—The relevance of instruction parallelization and optimal event scheduling is currently increasing. In particular, because of the high amount of computational power available tod...
163
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ERSA
2010
15 years 1 months ago
2010
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...