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» Computing stable models in parallel
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HPCA
2009
IEEE
16 years 2 months ago
Express Cube Topologies for on-Chip Interconnects
Driven by continuing scaling of Moore's law, chip multiprocessors and systems-on-a-chip are expected to grow the core count from dozens today to hundreds in the near future. ...
Boris Grot, Joel Hestness, Stephen W. Keckler, Onu...
CHI
2007
ACM
16 years 2 months ago
Towards a new method for the evaluation of reality based interaction
In this paper we present work toward a new method of evaluation for Reality-Based Interaction Styles that we call Cognitive Description and Evaluation of Interaction (CoDeIn). Thi...
Georgios Christou
HPCA
2002
IEEE
16 years 2 months ago
A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning
We propose a low overhead, on-line memory monitoring scheme utilizing a set of novel hardware counters. The counters act like pressure gauges indicating the marginal gain in the n...
G. Edward Suh, Srinivas Devadas, Larry Rudolph
HPCA
2001
IEEE
16 years 2 months ago
Reevaluating Online Superpage Promotion with Hardware Support
fipical translation lookaside buffers (TLBs)can map a far smaller region of memory than application footprints demand, and the cost of handling TLB misses therefore limits the per...
Zhen Fang, Lixin Zhang, John B. Carter, Wilson C. ...
106
Voted
ACSAC
2009
IEEE
15 years 8 months ago
SecureMR: A Service Integrity Assurance Framework for MapReduce
—MapReduce has become increasingly popular as a powerful parallel data processing model. To deploy MapReduce as a data processing service over open systems such as service orient...
Wei Wei, Juan Du, Ting Yu, Xiaohui Gu